OCR A-Level Computer Science

What the processor does

A processor runs a stored program. The program and the data it works on sit in main memory as binary patterns, and the processor repeatedly takes the next instruction from memory, works out what it means and carries it out. Everything a computer does is built from that one loop, and the parts of the processor are best understood by asking which step of the loop each of them serves.

The arithmetic logic unit, the control unit and the registers

The arithmetic logic unit (ALU) carries out arithmetic (addition, subtraction), logical operations (AND, OR, NOT, XOR), comparisons and bit shifts. It has no idea which instruction it is serving; it is given operands and told which operation to perform, and it returns a result together with some status information, such as whether the result was zero or negative.

The control unit (CU) decodes each instruction and then sends control signals to the other parts of the computer to make it happen: it tells the ALU which operation to perform, tells memory whether to read or write, and routes data along the right paths. It also keeps the steps in time with the clock, a regular electronic pulse that sets the pace of the whole processor.

A register is a tiny store built into the processor itself. It is far faster to reach than main memory, which is why the processor does all its work on values held in registers. Five registers matter in the model of a processor used here.

The MDR is sometimes called the memory buffer register, and the two names mean the same thing. General purpose registers, where they exist, hold other values the program is using.

Buses

A bus is a set of parallel wires that carries signals between components, and each wire carries one bit at a time. There are three.

The address bus carries the address of the memory location or device being accessed. It is one-way, from the processor outwards, because only the processor chooses where to read or write. The number of wires sets how many locations can be addressed: an address bus of $n$ lines can name $2^n$ locations, so 16 lines address $65\,536$ locations and 32 lines address $4\,294\,967\,296$ of them.

The data bus carries the data itself, or the instructions, between the processor, memory and input and output devices. It is two-way, because data goes out to memory on a write and comes in on a read. Its width sets how many bits can be moved at once, so a wider data bus moves more in each transfer.

The control bus carries the control signals from the control unit, such as a memory read, a memory write and the clock signal, and carries signals back to the processor, such as an interrupt request.

The fetch-decode-execute cycle

The processor repeats this cycle for as long as it is running. Register transfer notation describes exactly what moves where; square brackets mean "the contents of the memory location at that address".

Fetch

1. The address of the next instruction is copied from the PC to the MAR: $\text{MAR} \leftarrow \text{PC}$.
2. The PC is incremented so that it points to the following instruction: $\text{PC} \leftarrow \text{PC} + 1$.
3. The address in the MAR is placed on the address bus, a read signal goes out on the control bus, and the contents of that location come back along the data bus into the MDR: $\text{MDR} \leftarrow [\text{MAR}]$.
4. The contents of the MDR are copied to the CIR: $\text{CIR} \leftarrow \text{MDR}$.

The PC is incremented during the fetch, before the instruction has been run. That matters for a branch instruction, which overwrites the PC with a new address and so replaces the value that was just incremented.

Decode

The control unit examines the instruction in the CIR. An instruction is made of an opcode, which says what to do, and usually an operand, which is either a value or the address of a value. The control unit splits the two apart, works out which operation the opcode asks for and sets up the signals needed to perform it.

Execute

The instruction is carried out, and what happens depends on the opcode. The cycle then starts again from the fetch, with the PC already pointing at the next instruction.

For a load instruction the operand is sent to the MAR, the location is read into the MDR and the value moves to the ACC:

For an add instruction the same read is made and the ALU adds the value fetched to the ACC, leaving the result in the ACC. For a store instruction the operand goes to the MAR, the ACC is copied to the MDR and the MDR is written to memory. For a branch the operand is copied into the PC, so the next fetch comes from a different place.

A traced example

Suppose memory holds a four-instruction program beginning at address 0 and two data values. In the Little Man Computer instruction set, which is written out in full in its own note, LDA loads, ADD adds, STA stores and HLT stops.

The registers change as follows, with the PC starting at 0.

Location 6 now holds 12, which is the sum of the values at locations 4 and 5.

How the registers relate to assembly language

An assembly language instruction names exactly these operations. An instruction such as LDA is a load into the accumulator and STA a store from it, so a programmer writing assembly is directing the same register transfers described above. Branch instructions write a new value into the PC, which is the only way a program can depart from running in sequence. Because the program counter, the instruction register and the memory registers are part of the processor's own design, they are what differs between one processor family and another, and assembly language is tied to the processor it was written for for that reason.